1. Technical Field
The invention relates generally to testing of array structures such as a memory array, and more particularly, to reporting and/or analyzing test data from a plurality of tests of an array structure using a data array.
2. Background Art
In the semiconductor manufacturing industry, devices are tested prior to use. In many cases, the parts being tested have an array structure. For example, one part of a device that is tested is a memory array. Memory testers run a number of tests for each cell (or bit) of the memory array and record failures. Since memory arrays can include a very large number of cells (e.g., 2,097,152 cells for a 1024×2048 array), the amount of data collected can be immense. One approach to collect and organize the data is to log every cell failure to an American Standard Code for Information Interchange (ASCII) file, e.g., an ASCII comma delimited text file or comma separated value (csv) file. The data collected contains details of each failure such as failure locations, test type, failure type, etc. The large amount of data collected using this approach typically requires periodically pausing test execution and queries of the tester hardware during generation of the ASCII file. That is, memory test data is collected all at once. The result is a very large ASCII file which can take an excessive amount of time to generate.
One approach to address this situation is to limit the number of failures identified to a predefined maximum. Unfortunately, this approach mandates not capturing all of the failure data. In addition, this approach may add complexity in those cases where the number of failures reaches the predefined maximum. Another approach includes performing a binary dump of the data to a bit fail map, i.e., a physically viewable rendition (image) of the memory array including fail points. FIG. 1 illustrates a simplified bit fail map 10 that is a topographical representation of a 5×5 memory array including failing points (cells) F. Each bit fail map represents a different test applied across the memory array. Hence, each test requires another bit fail map. This approach is advantageous because it can be completed in a relatively short period of time compared to the logging of failures. Although all cell failure points are captured using this approach, other details such as the test type, failure type, etc., are not available.
The formats of the memory test data described above also negatively impacts data analysis.
In view of the foregoing, there is a need in the art for an improved solution to report and/or analyze test data from testing of an array structure.